WP3 results for the year 2

IMEC has published the results on its novel device architecture yielding 400 GHz fmax at the 2009 BCTM conference.  A SEM cross-section of the device is shown in Fig. 1.  The device fabrication starts with the epitaxial growth of collector and base regions, followed by etching of the extrinsic base, and reconstruction of the base contacts.  The self-alignment is realized using inside L-shaped spacers, followed by polyemitter processing.  The collector doping has been optimized compared to an earlier 300 GHz fmax version by introducing carbon in the collector.  The resulting ft and fmax are compared in Fig. 2. 

The DOTFIVE project partner from the University of Wuppertal has used at IHP an HBT-only evaluation version of a BiCMOS technology for benchmark circuit fabrication. Results of this preparation are presented at the ISSCC conference 2010.
In contrast to IHP’s 0.13m BiCMOS process (details see BCTM 2009), the following steps, affecting the HBT performance, were altered: The profile of the SiGe:C base layer was changed resulting in a lower base-sheet resistance while the collector current density was maintained approximately. The temperature of the final spike anneal was reduced. Furthermore, the wafers exhibit a 45° rotated substrate orientation, an enhanced sub-collector and a reduced salicide sheet resistance. The transistors achieve at VBE=0.7V a current gain of about 500 and demonstrate an open-base collector-emitter breakdown-voltage BVCEO of 1.7 V. Compared with the 0.13µm BiCMOS reference HBT, the peak fT /fmax values could be increased from 240 GHz / 330 GHz to approximately 250GHz/380GHz in this modified technology (see Fig. 3).